The present invention relates to the field of signal amplification and detection. More particularly, the present invention relates to a digital phase shift amplification and detection system and method for resolving small periods of time.
Electronic systems and circuits have made a significant contribution towards the advancement of modern technology, such as digital computers, calculators, audio devices, video equipment and telephone systems. In particular, electronic technologies are utilized in a number of applications to achieve advantageous results, such as increased productivity and reduced costs in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. It is often necessary for these electronic systems to resolve very small periods of time in order to produce these advantageous results.
Typically, the ability to resolve very small periods of time permits an electronic system to process higher frequency signals. The frequency of signals applied to an electronic system is an operating characteristic that has a significant impact on the functionality the system is capable of providing. The ability to process higher frequency signals usually means an electronic system is able to provide greater throughput and increased intelligence attributes.
In many instances, the applications that require very small periods of time to be resolved pose very significant challenges for most electronic systems and the timing requirements strain their performance capacity. In other instances, reliably resolving the very small periods requires very intricate and sensitive electronic circuits. Such intricate and sensitive electronic circuits are very expensive and in some instances they are an economic impracticality.
Typically, electronic digital circuits are very economic and operate reliably. Modem manufacturing techniques permit transistors (the basic circuit of electrical digital systems) to be constructed in a relatively inexpensive and extremely reliable manner. A transistor configured to operate as a switch consistently produces one of two possible output signal values. Since transistors can dependably generate one of two possible output signal values and because human logic tends to easily comprehend binary states (e.g. on/off, true/false, yes/no, etc.), most digital systems are designed to operate on the basis of discrete values comprising a logical 1 and a logical 0. Usually, the discrete logic values represent information and are manipulated by the circuits of an electronic digital system in a manner that provides solutions to an assortment of problems.
There is a great variety of digital circuit designs available for implementation in electronic circuits. Most electrical digital circuits comprise combinational circuits and sequential circuits. Combinational circuits have output values that are solely dependent on the value present at the inputs at the time the output is measured. However, in sequential circuits, the outputs at any particular time are dependent on both the present value of the inputs and the past history of the system. A common sequential circuits is a circuit referred to as a flip flop.
A flip flop is an example of a relatively inexpensive and extremely reliable electronic digital circuit. Two of the most fundamental flip flops are the NAND gate version and the NOR gate version. As with most digital electronic circuits, the gates are adapted to receive and analyze electrical signals that fall within two distinct ranges. Each of the distinct electrical ranges correspond to logical 1 and logical 0 binary values, which are analyzed in a conventional manner by utilizing Boolean principles. The basic characteristic of most flip flops operating under normal condition is that when certain control signals are applied to the flip flop, it toggles a specific value at an input through to an output in a specific amount of time and maintains (xe2x80x9cremembersxe2x80x9d) that output until a control signal indicates it should change. There are a variety of flip flop types available that operate in accordance with this basic characteristic.
FIG. 1A is a schematic of one embodiment of a NAND gate version flip flop 100. NAND gate version flip flop 100 comprises set port 101, clear port 102, a set NAND gate 103, a clear NAND gate 104, a result port 105 and an inverse port 106. Set NAND gate 103 inputs are coupled to set port 101 and inverse port 106. Set NAND gate 103 output is coupled to result port 105. Clear NAND gate 104 inputs are coupled to clear port 102, and result port 105. Clear NAND gate 104 output is coupled to inverse output 106.
Flip flop 100 operates in accordance with a typical truth table for NAND gate flip flops. The truth table in FIG. 1B illustrates the logical values at result port 105 and inverse port 106 for each of the possible logical values at set port 101 and clear port 102, when flip flop 100 is operated in accordance with manufacturer recommended timing constraints for normal operation. If set port 101 and clear port 102 are logical 1 then there is no change in the logical values at result port 105 and inverse port 106. If set port 101 is changed to a logical 0 value and clear port 102 to a logical 1 value, a short consistent time later, result port 105 will go to a logical 1 value and inverse port 106 will go to a logical 0 value. If set port 101 is switched to a logical 1 value and clear port 102 to a logical 0 value, the same short consistent time later, result port 105 will go to a logical 0 value and inverse port 106 will go to a logical 1 value. The flip flop will not operate properly if both set port 101 and clear port 102 are logical 0 since port 105 and inverse port 106 will both try to go to logical 0 which violates the output definition of flip flop 100 (result port 105 and inverse port 106 should have inverse logical value). Thus, appropriately controlling the inputs of a flip flop produces predetermined digital outputs within a short consistent time after a change in the inputs.
As previously indicated, flip flop 100 is an example of a digital circuit that is economical to manufacture and reliably produces discrete results in accordance with truth table in FIG. 1B when operated under normal conditions. However, when flip flop 100 is operated under normal conditions, its sensitivity to time shifts is determined by its operating characteristics. Most operating characteristics do not permit the resolution of very small time periods under normal operating conditions, for example the small timing differences that are countered when a small phase shift in a signal occurs. In addition, when flip flop 100 is operated under normal conditions, because it is a digital circuit it is not designed to provide many of the beneficial characteristics an analog system can provide.
Accordingly, what is required are economical and reliable digital systems and methods that are able to resolve relatively small time differences in a signal, including those that occur in very small phase shifts. It would be desirable to produce a system that could amplify and detect relatively small timing differences between changes in signals. The system should exhibit quasi analog characteristics and advantageously utilize such quasi analog characteristics. The present invention provides these advantageous functions.
The present invention is a digital system and method that is able to resolve very small timing differences in a signal, such as those that occur in very small phase shifts. It provides phase shift amplification of a relatively small input phase change to a relatively larger output phase shift. In addition, the present invention utilizes the amplified phase shift to detect differences in the timing of input signals, including small phase shifts. The present invention also exhibits other quasi analog characteristics and advantageously utilizes such quasi analog characteristics.
In one embodiment, the present invention relates to a digital phase shift amplification and detection system and method. A signal is applied to a digital phase shift amplifier including a flip flop operated in the metastable region which amplifies any timing changes in the signal. The amplified phase shift is fed into a detection circuit configured to detect the amplified timing differences in the input signal. The detection circuit is coupled to clock signals that are out of phase with the clock signal that triggers the metastable flip flop in the phase shift amplifier. The amount of phase shift between the clock signals impacts the position of nominal times in the metastable region. In addition, the greater the number of flip flops in the detection circuit that are coupled to clock signals that trigger the flip flop at a different time from any other flip flop in the detection unit, the greater the ability to differentiate and proportional sensitivity the present embodiment has to small timing differences in an input signal.
The present embodiment can be utilized to resolve very small increments of time. The capability of high resolution permits the present embodiment to be implemented in applications that provide an indication if a transition in a signal is at a nominal time, early, or late. It can also be used in applications that adjust a delay lock loop or applications that require fine tuning of a phase lock loop circuit.